Channelized and Unchannelized T3
Asynchronous T3 circuits have two modes that they can be leased in—channelized or unchannelized. The difference between the two of them is rather simple. The channelized T3 is composed of 28 T1s (672 DS0s) and has all the associated overhead and bit stuffing. Unchannelized T3 circuits are composed of a single, non-multiplexed DS3 signal. Because unchannelized T3 has no bit stuffing or overhead, all the bandwidth is available for user transmission.
A T3 is clocked at 44.736 Mbps. A channelized T3 offers 672 DS0s, so the maximum user rate is 43.008 Mbps, the difference being the overhead and bit stuffing.
On an unchannelized T3, the maximum user rate can be from 44.2 Mbps to 44.407 Mbps. The larger of the two rates is available if the C-bits are not needed for any management functions.
Channelized T3 circuits are normally deployed in a point-to-multipoint configuration because of the ease of distribution. Because you have 672 DS0s available to you, as long as your multiplexer supports it, you can groom and redirect any number of DS0s in any number of directions. This is a viable solution for a company that wants to manage all WAN connectivity from a central location. By doing so, the corporate office (CO) can provide more bandwidth to the offices that need it and manage the rest of the bandwidth efficiently. A topology example is given in Figure 7-1.
Unchannelized T3 circuits (44.2 Mbps) come in a single pipe of bandwidth. The unchannelized circuits are commonly deployed in a point-to-point configuration because no DS0s or DS1s can be separated from the signal stream. This is useful for applications that require a large amount of bandwidth between two locations such as university distance learning centers. A topology example is given in Figure 7-2.
Figure 7-2 Unchannelized T3 Link Between University Locations
University Remote Location Learning Center
Figure 7-2 Unchannelized T3 Link Between University Locations
University Remote Location Learning Center
T3 circuits are also used as the physical layer for technologies such as Asynchronous Transfer Mode (ATM) and Frame Relay. In these cases, the T3 circuit is the physical transport layer for the Layer 2 frame or cell switching technology. ATM uses an unchannelized T3 and requires a delineation mechanism to identify ATM cells; two methods are defined, physical layer convergence procedure (PLCP), which is adding a specific frame format (and overhead) and a header error control (HEC)-based delineation method. Although Frame Relay over T1 is more common, a standard for Frame Relay over T3 does exist.
Continue reading here: M12 Multiplexing
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