Configuring Hardware Based CoPP on the Catalyst 6500

The Cisco Catalyst 6500 switch with the Sup720/Sup32 supervisor engines offers predefined hardware rate limiters and supports hardware-based CoPP in conjunction with software-based CoPP. Hardware-based CoPP is implemented on the supervisor line card and on line cards that support distributed forwarding.

When a packet is destined for the control plane, it is first checked against the hardware rate limiters. If it matches one of those, it is limited to the configured rate, and hardware-based CoPP is not performed on the line card. If it does not match the hardware rate limiters, it is compared against the hardware CoPP policy and rate-limited on the line card into which it entered the switch.

Finally, the packet is again subjected to the CoPP policy (but now in software mode), because even though it has already been validated on the line card, it might not agree with the aggregated packet flow from all the line cards.

NOTE Because of how hardware-based CoPP is implemented on the Catalyst 6500 Sup720/Sup32 supervisors, a packet matching one of the hardware rate limiters bypasses the hardware-based CoPP policy on the switch. The CoPP, however, processes it in software mode. This means that you can either use hardware-based limiters or hardware-based CoPP for specific traffic, but not both.

Figure 13-3 shows how flows are first rate-limited in hardware mode on each line card and then subjected to software-based CoPP.

Figure 13-3 Cisco Catalyst 6500 CoPP Support

The aggregate traffic from the line cards is processed again by centralized Software CoPP. The aggregate traffic can be N times larger than the configured rate limit, where N is the number of distributed line cards.

The aggregate traffic from the line cards is processed again by centralized Software CoPP. The aggregate traffic can be N times larger than the configured rate limit, where N is the number of distributed line cards.

Each line card implements Hardware rate limiters or the Hardware CoPP policy independently.

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HW Control

HW Control

HW Control

Plane Policing

Plane Policing

Plane Policing

Traffic to CPU

Traffic to CPU

Traffic to CPU

Traffic to CPU

Traffic to CPU

Continue reading here: Hardware Rate Limiters

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