class-map Strict-priority match cos 5
class-map High-priority match cos 4 6 7
class-map Low-priority match cos 0 1 2 3
Routers can also match the three CoS bits in 802.1Q headers or priority bits in the ISL header. These bits can be used in a LAN-switched environment to provide differentiated quality of service.
This is demonstrated in the example. In the first class map, Strict-priority, packets will be matched if they have a CoS value of 5.
In the second class map example, High-priority, packets will be matched if they have a CoS value of either 4, 6, or 7.
And in the last class map example, Low-priority, packets will be matched if they have a CoS value of any of 0, 1, 2, or 3.
match cos cos-value [cos-value cos-value cos-value]
(Optional) Specific IEEE 802.1Q/ISL CoS value. The cos-value is from 0 to 7; up to four CoS values can be specified in one match cos statement.
This topic describes the Cisco IOS commands that are required to classify IP packets using access lists with MQC.
Access lists were originally used for filtering of inbound or outbound packets on interfaces. They were later reused for filtering of routing updates and also for classification with early QoS tools, such as priority queuing (PQ), custom queuing (CQ), and traffic shaping.
Access lists are still one of the most powerful classification tools. Class maps can use any type of access list (not only IP access lists).
Access lists have a drawback: Compared to other classification tools they are one of the most CPU-intensive. For this reason, access lists should not be used for classification on high-speed links where they could severely impact performance of routers. Access lists are typically used on low-speed links at network edges, where packets are classified and marked (for example, with IP precedence). Classification in the core is done based on the IP precedence value.
However, access lists may be efficiently used for classification purposes on Catalyst switches, as all classification operations (with the exception of NBAR classification on Catalyst 6500s) on Catalyst switches are performed in hardware, without any incremental CPU load.
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